Developing and implementing low-k ILD based ICs requires complementary and compatible photolithography and etching processes to pattern devices that will not attack underlying layers critical to device performance. For example, tungsten (W) contacts in transistor terminals (e.g., gates), which may be formed as plugs in deep vias by etching through SiO2, etch-stops, low-k ILD and metal hard masks, may be attacked using conventional etches and final resist cleaning processes. In particular, during low-k ILD patterning TiN metal hard masks (HM) removal can occur. In addition, TiN etchants may also attack and etch W.
Via 0 (V0) contacts are contact vias which are used, for example, as vertical interconnects between the source/drain of CMOS devices and the metal lines in multilevel interconnect schemes. The current post patterning cleaning schemes as applied to a first metal layer (M1) deposited on a V0 have an extremely narrow process window due to the requirements of being able to remove both the metal HM (Ti or TiN), photoresist, and residual etch polymer while simultaneously not etching W, Cu or the low-k ILD. The combination of TiN HM with the underlying W is particularly troublesome as the resist cleans used in the patterning process to form several metal layers (e.g., M1, M2, M3 and M4) all attack W.
One current approach to overcoming one aspect of the above problem is the use of Ti HM. Various process are known in the art that utilize resist cleans which are compatible with W, Cu, and low-k ILD and which are also capable of simultaneously removing Ti HM. However, the Ti HM is opaque, making it difficult to register mask alignment with structures formed in previous photolithographic steps. As dimensional scaling continues, maintaining relative dimensional registration accuracy is becoming an increasingly demanding operation.
There is a need, therefore, for a method of fabricating deep W contact vias in low-k ILD ICs which can endure attacks from resist cleans and metal HM removal steps, and which provides transparency to enable improved photolithographic registration.
Features, elements, and aspects of the invention that are referenced by the same numerals in different figures represent the same, equivalent, or similar features, elements, or aspects, in accordance with one or more embodiments.